The present invention relates to a chip ID applying method for specifying positions on a wafer where semiconductor chips are fabricated.
An integrated circuit is generally manufactured in accordance with the following flow.                (1) A large number of chips are fabricated on a wafer.        (2) After the formation of each circuit on the wafer, various electrical function tests are conducted in a state in which the wafer is held as it is.        
The process steps (1) and (2) executed so far are generally called a pre-process or wafer process. The following process steps (3) through (5) are generally called a post-process or package process.
(3) The individual chips are separated from one another to bring them into fractionization.
(4) The fractionized chips are respectively encapsulated in plastic or a ceramic package.
(5) After encapsulation of each chip in the package, the product is completed as the integrated circuit through a final test.
The pre-process for building a large number of chips in the wafer shown in the previous process step (1) will next be explained. A technique called photolithography is normally used to build each circuit in the wafer in the pre-process. This technique is the technology of allowing circuit patterns formed in a mask (reticle) to be exposed onto the wafer using light and thereby transferring the circuit patterns. Since circuit patterns corresponding to plural chips each having the same circuit pattern are normally fabricated in a mask (e.g., 4 chips wide×4 chips deep), the circuit patterns corresponding to plural chips (e.g., 4×4=16 chips) can be transferred by one exposure (shot).
Incidentally, the circuit patterns cannot be normally transferred over the whole area of one wafer by one shot alone. Therefore, in order to transfer the circuit patterns over the whole area of the one wafer, a stage with the wafer placed thereon is moved in the horizontal and vertical directions and the shot is repeated plural times, thereby transferring the circuit patterns onto the whole surface of the wafer. This system is called “a step-and-repeat system”. In the present photolithography process, only circuit patterns corresponding to one wiring layer per process step even at the maximum can be transferred. However, a complex structure or circuit having a number of wiring layers can be fabricated by repeating the photolithography process many times. In the integrated circuit manufacturing process, a few tens to a few hundreds of chips each having circuit patterns exactly identical to one another are fabricated on one wafer while the lithography process is being repeated again and again in this way.
Incidentally, if it is possible to recognize whether each individual completed integrated circuit corresponds to a chip formed at any position on the wafer, then the dependence of the degree of variations in various electrical characteristics on wafer in-plane positions, and the like can be examined. Therefore, information indicative of whether each individual chip being fabricated at any location in the wafer in-plane becomes information important in light of quality management. Since such information is of information descriptive of production histories different every chip, the information is called a chip ID in the sense that it is ID for each individual chip. The information is fabricated or built in each integrated circuit as electrically-indelible information.
Since the chips identical to one another are manufactured in large quantities at a time in the conventional integrated circuit manufacturing method as already described above, it is difficult to build the chip IDs at a pre-process stage. Therefore, the conventional method of manufacturing the semiconductor integrated circuit needed to provide an exclusive special-purpose process step within the post-process. Described specifically, IDs set for each chip are written by cutting off laser fuses or electric fuses provided inside the chips every chip.
For instance, only a first fuse is cut off when fabricated at a position A on a wafer, and first and second fuses are cut off when fabricated at a position C. This fuse cutting-off process step is normally executed as a process step accompanying the electrical function tests at the previously-mentioned process step (2). A problem arises in that since the fuse cutting-off process step needs to cut off the fuses different every chip, their cut-off must be carried out in order one chip by one chip and hence a long period of time is required.
A patent document 1 (Japanese Unexamined Patent Publication No. Hei 5 (1993)-175093) discloses a method of specifying the positions of chips in a wafer without using fuses. Here, underlaying marks for wafer-in chip position indication patterns are formed in parts of device areas of the respective chips by exposure at exposure processing in a wafer-in chip final wiring process. Thereafter, shots different in position with respect to the underlaying marks are formed by exposure and the positions of the chips in the wafer are specified by combinations of the underlaying marks and the shots.
In the method shown in the above patent document 1, however, there is a need to execute dedicated process steps in addition to the need for dedicated patterns because the transfer positions of the shots exposed onto the underlaying marks are changed in order. As a result, there is a fear that complexity of a manufacturing process and an increase in manufacturing cost are encountered.